1. Field of the Invention
This invention relates to a data processing apparatus, and more particularly to an instruction prefetching circuit for a data processing apparatus.
2. Description of the Prior Art
A conventional instruction prefetching circuit has a page-over detecting circuit disposed at the input or the output of the instruction address register for detecting whether or not an address of a prefetched instruction goes over the boundary of the page (hereinafter referred to as page-over).
When a page-over is detected, the value (logical page number) of the effective address register in which an effective address of the instruction being executed at the point of time is stored is incremented by one using an address adder or some other adding means and the TLB (address converting buffer) is accessed so that a physical page number is determined. The thus determined physical page number is replaced by a physical page number portion of the instruction address register in which the physical page number before the page-over is stored.
By the way, in the conventional page-over processing method, in order to determine a physical page number in a physical address after a page-over has occurred, at least two cycles are required including a physical page number adding cycle and a TLB indexing cycle. Consequently, an overhead loss of at least two cycles is caused in instruction prefetching by the page-over processing. Accordingly, the conventional page-over processing method has a drawback that supply of an instruction is retarded by two cycles and execution of the instruction is retarded at least by two cycles.